In electronic circuit applications supporting high-voltage switching operations, a circuit called a “level shifter” is used to transfer signals between circuit networks at different voltage levels. When a level shifter is combined with an inverter, the level shifter performs the function of converting a logic signal operating in the voltage range from 0 to V1 into an output signal operating in the voltage range from 0 to V2.
Furthermore, a level shifter also refers to a circuit for simply transferring a voltage level, rather than transferring a logic signal. In this case, when a predetermined logic condition is satisfied, a voltage level on an input side is transferred to an output side via a pass switch, and then the operation of raising or stepping down a voltage using a circuit, such as a bootstrap circuit or charge pump, is performed.
Examples of the typical circuits of such high-voltage level shifters are disclosed in U.S. Pat. No. 5,160,854 entitled “Single-Drive Level Shifter with Low Dynamic Impedance,” U.S. Pat. No. 6,727,742 entitled “High-Voltage Level Shifting Circuit with Optimized Response Time,” etc.
U.S. Pat. No. 6,727,742 discloses an example of the circuit of a conventional high-voltage level shifter, which is shown in FIG. 1.
Referring to FIG. 1, a level shifter circuit is shown, whose output voltage OUT swings between VBOOT and VPHASE in response to an input control signal Φ.
VBOOT, i.e., the upper limit of the output voltage VOUT, is generally high voltage power equal to or higher than 40 to 50 V, and VPHASE, i.e., the lower limit of the output voltage VOUT, is generally power having a voltage level lower than that of VBOOT by a predetermined difference. Generally, high-voltage level shifters are widely used in power devices that drive high current. When power devices are implemented using semiconductors, Double Diffused Metal Oxide Semiconductor (DMOS) transistors are widely used.
DMOS transistors include Vertical DMOS (VDMOS) transistors and Lateral DMOS (LDMOS) transistors. It is known that they have a high drain-source breakdown voltage ranging from about 40 to about 50 V in common, but it is very difficult to increase their gate-source voltage to a level of tens of volts because the gate-source voltage is determined based on the thickness of the channel oxide of the transistors.
Accordingly, a high-voltage level shifter is designed not to exceed the threshold of the gate-source voltage in order to ensure the safe operation of a DMOS transistor. For example, when the threshold of the gate-source voltage of the DMOS is 10 V in FIG. 1, the difference between VBOOT and VPHASE is determined to be equal to or less than 10 V.
To obtain electric potential VPHASE having a predetermined difference with VBOOT, the combination of a resistor R1 and a current source Idd and a clamping circuit M3 are widely used, as shown in FIG. 1.
When an input control signal Φ becomes ON, the current source Idd operates and accordingly a switch MHV is turned on, with the result that current Idd flows through the switch MHV. In this case, since all or part of the current Idd flows through the resistor R1, a difference in voltage occurs between VBOOT and a node 110 due to a voltage drop between both ends of the resistor R1. Since the node 110 corresponds to the voltage Vg of the gate nodes of M1 and M2, the transistor M1, i.e., a PMOS, is turned on, and thus output voltage OUT has the voltage level of VBOOT. Meanwhile, when the transistor M3 is turned on, a difference corresponding to the threshold voltage VT,M3 of the transistor M3 is present between the voltage VPHASE of the gate node of M3 and the voltage Vx of the node 110, i.e., the source node of M3. That is, a condition is set up by Equation 1 below:Vx=VPHASE−VT,M3  (1)
When the transistor M3 is turned off when the potential difference between VPHASE and Vx reaches VT,M3, the current Idd flows through only the resistor R1. In this case, the voltage Vx of the node 110 satisfies the condition of Equation 2 below:Vx=VBOOT−Idd·R1  (2)
Accordingly, VPHASE, i.e., the lower limit of the output voltage OUT, satisfies Equation 3 below:VPHASE=VBOOT−Idd·R1+VT,M3  (3)
That is, it can be seen that the difference between VPHASE, i.e., the lower limit of the output voltage VOUT, and VBOOT is determined by the current source Idd, the resistor R1 and the threshold voltage VT,M3 of the transistor M3.
In contrast, when the input control signal Φ becomes OFF, the current source Idd is cut off. In this case, since the current flowing through the resistor R1 becomes 0 when a sufficiently long time has passed, the voltage between both ends of the resistor R1 becomes 0 V. That is, Vx=VBOOT. In this case, the drain-source voltage of the transistor M3 is 0 V, and thus current does not flow through the transistor M3 still. Furthermore, since the voltage Vx is VBOOT and high, the transistor M2 is turned on, and thus the output voltage OUT has the voltage level of VPHASE.
Although the circuit of FIG. 1 would operate according to the above-described method when observation is conducted over a long time interval, a problem arises in that the operation is actually delayed due to the parasitic capacitances Cr and Cp of the node 110 shown in FIG. 1. In this case, Cr denotes the parasitic capacitance of the resistor R1, and Cp denotes the parasitic capacitance of the switch MHV.
When the input control signal Φ transitions from an OFF state to an ON state, the voltage Vx of the node 110 must drop from VBOOT to (VBOOT−Idd·R1). However, in practice, the transition from OFF state to ON state is slowly performed with an RC delay due to time constant R1·(Cr+Cp). In the same manner, when the input control signal Φ transitions from an ON state to an OFF state, the voltage Vx of the node 110 must rise from (VBOOT−Idd·R1) to VBOOT. In practice, the transition from ON state to OFF state, Vx slowly reaches a steady state due to the time constant R1·(Cr+Cp).
This means that duration of a transient response increases considerably. In this case, when Vx has an intermediate level between VBOOT and VPHASE, there is a risk that the voltage of VPHASE transitions to a value close to VBOOT for the reason that the transistors M1 and M2 are turned on at the same time, or the like. To overcome this risk, inconvenience in circuit design arises in that reservoir capacitance corresponding to the node of VPHASE must be considerably high.
FIG. 2 is a diagram showing an improvement over the circuit of FIG. 1 proposed in U.S. Pat. No. 6,727,742.
Referring to FIG. 2, the gate node of a clamping transistor M3 is connected to output voltage OUT, not VPHASE. Accordingly, when an input control signal Φ remains in an ON state for a long time, Vx is clamped from VBOOT, i.e., the voltage level of the output voltage OUT, not from VPHASE. That is, Equation 4 below is formulated:Vx=VBOOT−VT,M3  (4)
According to this scheme, the swing range of Vx is reduced compared to Idd·R1 of FIG. 1, and accordingly the effect of speeding up the switching of the level shifter is achieved.
However, despite the improved circuit of FIG. 2, a problem still arises in that node 210 suffers from the delay of a time response attributable to an RC time constant.
Furthermore, another problem arises in that the improved circuit of FIG. 2 undergoes more difficulty in matching the threshold voltage characteristic of the transistors M1, M2 and M3 than the circuit of FIG. 1.
In the conventional art shown in FIG. 2, when the input control signal Φ transitions from an ON state to an OFF state (when Vx rises from a low voltage to a high voltage), the time required can be reduced, but this conventional art cannot provide a fundamental solution. As a result, a problem arises in that the rising and falling characteristics of Vx are determined based on an RC time constant.
Furthermore, the conventional art shown in FIG. 2 is problematic in that since the lower limit of Vx is determined to be (VBOOT−VT,M3), the transistor M2 is turned off at the lower limit of Vx and thus can achieve its intended purpose only if the threshold voltage VT,M2 of the transistor M2 is considerably high. For this purpose, the conventional art has a problem in that the condition of Equation 5 below must be satisfied:VT,M2>VBOOT−VT,M3−VPHASE  (5)
In contrast, since the transistor M1 can achieve its intended purpose only if the transistor M1 is turned on at the lower limit of Vx, a problem arises in that the threshold voltage VT,M1 of the transistor M1 must satisfy Equation 6 below:VT,M1<VT,M3  (6)
That is, the conventional art is problematic in that it cannot be a fundamental solution to an RC time delay and also it is very difficult to match the threshold voltage characteristics of transistors.
As a result, there is a demand for a circuit design technique that can overcome the delay of a time response attributable to an RC time constant while effectively protecting transistors in a high-voltage switching circuit or level shifting circuit as in the conventional art.